1. Field of the Invention
The present invention relates to a method of etching a surface layer portion of a silicon wafer, more particularly, to a method of etching a surface layer portion of a silicon wafer that is suitable as a method of etching a surface layer portion of a silicon wafer to analyze metal contamination of the silicon wafer. Still more particularly, the present invention relates to an etching method that is capable of etching a surface layer portion of a silicon wafer in the direction of depth thereof with in-plane uniformity.
The present invention further relates to a method of analyzing metal contamination of a silicon wafer employing the above etching method.
2. Discussion of the Background
As semiconductor devices have become smaller and more highly integrated in the field of semiconductor manufacturing, trace metal impurities on the surface of the semiconductor substrate have been reported to affect device characteristics by producing leak defects and gate oxide integrity defects, shortening service lifetime, and the like. Further, not just contamination by metal impurities on the surface of the semiconductor substrate, but trace metal impurity contamination in areas of the surface layer of a semiconductor wafer on which device structures such as shallow trenches, sources, and drains are formed are also viewed as problems that affect device characteristics.
Conventionally, quantitative analysis methods in which the surface layer portion of a silicon wafer is dissolved in an acid solution, the acid solution is diluted or concentrated, and then the diluted or concentrated solution is subjected to quantitative analysis by atomic absorption spectrometry (AAS) or inductively coupled plasma mass spectrometry (ICP-MS) (referred to as “liquid phase etching methods” hereinafter), have been employed as methods of evaluating metal impurities on the surface and surface layer portions of silicon wafers. However, when employing the liquid phase etching method, uniform etching of the surface layer of a silicon wafer requires a large quantity of acid solution. Accordingly, inadequate sensitivity results from dilution of the metal impurity concentration by the large quantity of acid solution employed. Further, decreased sensitivity results from a heightened analysis background because of the introduction of contaminants from the acid solution itself. Both of these hinder highly sensitive analysis in the field of semiconductor manufacturing field, in which the evaluation of extremely small quantities of metal impurities is required.
Accordingly, methods in which the surface layer portion of a silicon wafer is decomposed with an acid vapor (etching gas), the decomposition residue is collected, and then the collected residue is subjected to quantitative analysis by AAS or ICP-MS (referred to as “vapor phase etching methods” hereinafter) have been proposed in recent years as substitute methods for the liquid phase etching methods. Such methods are proposed in Document 1 (Japanese Patent No. 3,473,699) as well as English language family members US2008/047934 A1, U.S. Pat. No. 7,686,973, and US2004/232111 A1, and Document 2 (Japanese Patent No. 3933090), which are expressly incorporated herein by reference in their entirety.
The vapor phase etching method described in Document 1 affords advantages in that only a small quantity of acid solution is needed for etching and the quantity of contamination introduced by the acid solution itself is much smaller than in liquid phase etching. However, in vapor phase etching methods in general, the acid (acid vapor) and semiconductor substrate react slowly. Accordingly, there is a problem in the form of low analysis sensitivity due to the low depth of etching per unit time. Although it is possible to increase the depth of etching by conducting the etching reaction for an extended period, analysis requiring long periods is undesirable from the perspective of enhancing productivity.
By contrast, in the vapor phase etching method described in Document 2, the surface of the silicon wafer is etched with a vapor produced from a mixed acid comprising hydrofluoric acid, nitric acid, and sulfuric acid (and optionally containing pieces of silicon). Nitric monoxide, NO, that is produced by the reaction serves as a catalyst, thereby shortening the etching time.
However, it is difficult to control the quantity of gas that is generated in conventional vapor phase etching methods, including the method described in Document 2. Thus, the amount of etching of the wafer tends to be nonuniform within the surface. This results in reduced analysis precision in the course of depth profile analysis of metal impurity distribution. It also becomes difficult to accurately compare metal contamination of the surface layer portions between wafers. Still further, when selectively analyzing just the epitaxial layer present on the extreme outer layer portion of a wafer, some portions within the surface end up being etched all the way to the underlayer of the epitaxial layer when the etching amount of wafer is nonuniform within the surface, resulting in a substantial drop in analysis precision.